元器件交易網訊 4月23日消息，據外媒報道，
其中，DSP模塊符合IEEE 754標準，該模塊也將用于Stratix 10 FPGA中。
Arria運算能力達到1.5Tflop，Stratix運算能力為10Tflop。
“設計者可以選擇固定模式或浮點模式，且浮點塊可以與已有設計向后兼容。用戶可以采用這些FPGA解決大數據分析、制作油氣業抗震模型、進行金融模擬。”
浮點模塊采用的包括示范和基準在內的浮點設計流程將于下半年推出。
20nm的Arria 10采用兩枚ARMCortex-A9核心，串行收發器速度達28.3Gbit/s，母板最高支持17.4Gbit/s，并支持2.666Gbit/s DDR4。（元器件交易網毛毛 譯）
以下為原文：
Altera adds hard floating point to FPGAs
Altera is shipping Arria 10 FPGAs withhardened floating-point DSP blocks, but customers will have to wait for designflows.
The DSP block, which is IEEE 754-compliant,will also be in Stratix 10 FPGAs.
Up to 1.5 Tflop is claimed in Arria and 10Tflop in Stratix.
“Designers are able to choose either fixed or floating-point modesand the floating point blocks are backwards compatible with existing designs,”said Altera. “The inclusion enable customers to use FPGAs to address problemsin big data analytics, seismic modeling for oil and gas industries andfinancial simulations.”
Floating-point design flows, includingdemonstrations and benchmarks, for the floating-point blocks will be availablein the second half of this year.
“Customers can start designing today with Arria 10 FPGAs using softimplementations of floating point and then seamlessly migrate to hardenedfloating point implementation when the design flows are available.”
The firm’s DSP Builder Advanced Blocksetwill offer a model-based design flow allowing designers to go from systemdefinition and simulation to system implementation using MathWorks Simulink.
20nm Arria 10 can also include a dual-corehard ARM Cortex-A9, serial transceivers up to 28.3Gbit/s, backplane support upto 17.4Gbit/s, and support for DDR4 at 2.666Gbit/s.
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